The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device which has a memory chip sealed with resin material permitting no passage of ultraviolet rays, and into which desired data can be written only once.
An EPROM is well known as a nonvolatile semiconductor memory device of the type in which data can be erased by ultraviolet rays and new data can then be written. The EPROM comprises a ceramic package having a glass window, and a semiconductor memory chip sealed within the package. In order to erase data in the memory chip, ultraviolet rays are applied to the chip through the glass window. In order to write new data into the memory chip, electric signals are supplied to the package pins connected to the memory chip.
Recently the demand for one-time programmable read-only memories (or OTPROMs) has been increasing in the market of nonvolatile semiconductor memory devices. An OTPROM is characterized in that a semiconductor memory chip, which is similar to one used in the EPROM, is sealed within a plastic package without a glass window. Since ultraviolet rays cannot be applied to the memory chip, the data stored in the chip cannot be erased. Nor can new data be written into the memory chip. In other words, data can be written only once into the chip. Nonetheless, an OTPROM is advantageous over an EPROM. It can be manufactured at lower cost since the plastic package is less expensive than the ceramic package having a glass window.
A market search has shown that about 80% of all EPROMs used thus far have never undergone a data-rewriting process. It would obviously better to replace as many EPROMs as possible with less expensive OTPROMs. In view of this, it can be predicted that OTPROMs will be dominantly used in the future.
However, the OTPROMs hitherto known have a drawback. Once an OTPROM has been completed, it is no longer possible to write data into the memory cells of the OTPROM. Hence, any test data cannot be written in the cells in order to check the reliability of the OTPROM. One of the important tests that must be performed on OTPROMs is to determine the address access time, i.e., the time which has elapsed from the addressing of any memory cell until the data-transfer onto the data output line to which the cell is coupled. In order to measure the memory access time of the OTPROM, test data must be stored into memory cells, Since no data can be written in the memory cells after the OTPROM has been completed, the memory access time cannot be determined at all.
The memory cells of an EPROM, and the method of measuring the address access time of an EPROM will be explained to facilitate the understanding of the present invention.
An EPROM has memory cells arranged in rows and columns. Each of these memory cells comprises an n-channel, floating gate MOS transistor. FIG. 1 is a schematical, cross-sectional view of this MOS transistor. As is shown in FIG. 1, the MOS transistor comprises n.sup.+ -type source region 10 and n.sup.+ -type drain region 12, both formed in the surface region of p-type semiconductor substrate 14. That surface portion of substrate 14 which is located between source region 10 and drain region 12 serves as channel region 14A. Insulation film 18 is formed mainly on this channel region 14A and partly on source region 10 and drain region 12. Floating gate 16 is formed on insulation film 18. Insulation film 22 is formed on floating gate 16. Control gate 20 is formed on insulation film 22. Source region 10 and substrate 14 are connected to a power terminal at ground potential of, for example, 0 volt.
Each memory cell of the EPROM stores data corresponding to the electric charge within the floating gate 16 of the MOS transistor shown in FIG. 1. More specifically, the memory cell stores data "1" when floating gate 16 is discharged, and stores data "0" when floating gate 16 is charged. The EPROM is delivered from the factory, with its all memory cells storing data "1". In other words, the floating gates 16 of all memory cells are in discharged state when the EPROM is delivered from the manufacturer to the user. The user selects some of the memory cells, and writes data "0" into the selected memory cells, thus programming the EPROM.
The programming of the EPROM is performed in the following way. A programming voltage VPP (e.g., 12.5 V) is applied through the power source pin of the EPROM package to a data-writing circuit provided within the EPROM. Then, the data-writing circuit sets drain region 12 and control gate 20 of each selected memory cell at high potential of, for example, 8 V and 12.5 V, respectively. A current thereby flows through the current path of the MOS transistor forming the selected memory cell. Subsequently, hot electrons are generated within that portion of channel region 14A which is adjacent to drain region 12. These hot electrons are accelerated by the electric field extending between control gate 20 and substrate 14, and are injected into floating gate 16. As a result, floating gate 16 discharged, and its potential falls. The threshold voltage VTH of the MOS transistor therefore rises. More precisely, threshold voltage VTH is changed from a first predetermined level (e.g., 2 V), which is lower than power source voltage VCC (e,g., 5 V), to a second predetermined level (e.g., 5 V) equal or higher than power source voltage VCC.
To read data from the EPROM, power source voltage VCC is applied to the power source pin of the EPROM package, whereby the drain region 12 and control gate 20 of each selected memory cell are set to the potential equal to power source voltage VCC. The logic value of the data stored in the selected memory cell is detected from the change in the drain voltage, which has been caused by the current flowing through the current path of the MOS transistor. When threshold voltage VTH is at the first predetermined level, the MOS transistor is turned on, whereby data "1" is read from the memory cell. Conversely, when threshold voltage VTH is at the second predetermined level, the MOS transistor is turned off, whereby data "0" is read from the memory cell.
The change .DELTA.VTH of threshold voltage VTH cell depends on the charging period TPW (or programming pulse width) of floating gate 16. The relationship between .DELTA.VTH and cell log (TPW) is shown in FIG. 2. As is evident from FIG. 2, the longer the charging period TPW, the greater the change .DELTA.VTH cell.
The EPROM is programmed by intelligent program method, as is commonly practiced. In this program method, a programming voltage VPP is applied to the package pin of the EPROM, in the form of a pulse having a prescribed duration, thereby charging the floating gate 16 of each selected memory cell to such extent that data "0" can be read from the memory cell. When it is ascertained that floating gate 16 has been charged to this extent, an additional pulse of voltage VPP is supplied to the package pin, thus further charging floating gate 16. Hence, data "0" can be more reliably read from the selected memory cell.
A so-called "checker pattern" is used to measure the address access time of the EPROM. The checker pattern is data consisting of "1" bits and "0" bits alternately stored in the memory cells of each row, and "1" bits and "0" bits alternately stored in the memory cells of each column. In other words, when data "1" is stored in memory cell M(i,j) of the ith row and the jth column (i=2, 4, 6, 8 . . . ; i=2, 4, 6, 8 . . . ), data "0" is stored memory cells M(i, j-1), M(i, j+1), M(i-1, j), and M(i+1, j). The address access time is measured after this checker pattern has been preset in the memory cell array. Data "1" or data "0" is read through alternate data lines as all memory cells are sequentially designated. The period which the potential of each data line requires to change completely. The checker pattern is used to read "1" data and "0" data by turns since the potential of each data line must change when the data being read out through the data line falls from "1" level to "0" level, or rises from "0" level to "1" level.